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DS90LV049 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. DS90LV049
Description  3V LVDS Dual Line Driver with Dual Line Receiver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS90LV049 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Electrical Characteristics (Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
LVCMOS Output DC Specifications (Receiver Outputs)
V
OH
Output High Voltage
I
OH = -0.4 mA, VID= 200 mV
R
OUT
2.7
3.3
V
V
OL
Output Low Voltage
I
OL = 2 mA, VID = 200 mV
0.05
0.25
V
I
OZ
Output TRI-STATE Current
Disabled, V
OUT =0VorVDD
-10
±1
+10
µA
General DC Specifications
I
DD
Power Supply Current (Note 3)
EN = 3.3 V
V
DD
21
35
mA
I
DDZ
TRI-State Supply Current
EN=0V
15
25
mA
Switching Characteristics
V
DD = +3.3V ± 10%, TA = −40˚C to +85˚C (Notes 4, 13)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS Outputs (Driver Outputs)
t
PHLD
Differential Propagation Delay High to Low
R
L = 100
(Figure 2 and Figure 3)
0.7
2
ns
t
PLHD
Differential Propagation Delay Low to High
0.7
2
ns
t
SKD1
Differential Pulse Skew |t
PHLD −tPLHD|
(Notes 5, 7)
0
0.05
0.4
ns
t
SKD2
Differential Channel-to-Channel Skew
(Notes 5, 8)
0
0.05
0.5
ns
t
SKD3
Differential Part-to-Part Skew (Notes 5, 9)
0
1.0
ns
t
TLH
Rise Time (Note 5)
0.2
0.4
1
ns
t
THL
Fall Time (Note 5)
0.2
0.4
1
ns
t
PHZ
Disable Time High to Z
R
L = 100
(Figure 4 and Figure 5)
1.5
3
ns
t
PLZ
Disable Time Low to Z
1.5
3
ns
t
PZH
Enable Time Z to High
1
3
6
ns
t
PZL
Enable Time Z to Low
1
3
6
ns
f
MAX
Maximum Operating Frequency (Note 16)
200
250
MHz
LVCMOS Outputs (Receiver Outputs)
t
PHL
Propagation Delay High to Low
(Figure 6 and Figure 7)
0.5
2
3.5
ns
t
PLH
Propagation Delay Low to High
0.5
2
3.5
ns
t
SK1
Pulse Skew |t
PHL −tPLH| (Note 10)
0
0.05
0.4
ns
t
SK2
Channel-to-Channel Skew (Note 11)
0
0.05
0.5
ns
t
SK3
Part-to-Part Skew (Note 12)
0
1.0
ns
t
TLH
Rise Time(Note 5)
0.3
0.9
1.4
ns
t
THL
Fall Time(Note 5)
0.3
0.75
1.4
ns
t
PHZ
Disable Time High to Z
(Figure 8 and Figure 9)
3
5.6
8
ns
t
PLZ
Disable Time Low to Z
3
5.4
8
ns
t
PZH
Enable Time Z to High
2.5
4.6
7
ns
t
PZL
Enable Time Z to Low
2.5
4.6
7
ns
f
MAX
Maximum Operating Frequency (Note 17)
200
250
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VTH,VTL,
VOD and ∆VOD.
Note 3: Both, driver and receiver inputs are static. All LVDS outputs have 100
Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped
capacitive load.
Note 4: All typical values are given for: VDD = +3.3 V, TA = +25˚C.
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: The DS90LV049’s drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. The
typical range of the resistor values is 90
Ω to 110 Ω.
Note 7: tSKD1 or differential pulse skew is defined as |tPHLD −tPLHD|. It is the magnitude difference in the differential propagation delays between the positive going
edge and the negative going edge of the same driver channel.
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