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DS90LV032A Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. DS90LV032A
Description  3V LVDS Quad CMOS Differential Line Receiver
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90LV032A Datasheet(HTML) 4 Page - National Semiconductor (TI)

  DS90LV032A Datasheet HTML 1Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 2Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 3Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 4Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 5Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 6Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 7Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 8Page - National Semiconductor (TI) DS90LV032A Datasheet HTML 9Page - National Semiconductor (TI)  
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Parameter Measurement Information (Continued)
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 5. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers . The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100
Ω. A termination resistor of
100
Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termina-
tion resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and
other impedance discontinuities as well as ground shifting,
noise margin limits, and total termination loading must be
taken into account.
DS100067-5
CL includes load and test jig capacitance.
S1 =VCC for tPZL, and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
FIGURE 3. Receiver TRI-STATE Delay Test Circuit
DS100067-6
FIGURE 4. Receiver TRI-STATE Delay Waveforms
Balanced System
DS100067-7
FIGURE 5. Point-to-Point Application
www.national.com
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