256K x 16 Static RAM
CY7C1041B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 23, 2001
1CY7C1041B
Features
• High speed
— tAA = 12 ns
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400
µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The
CY7C1041B
is
available
in
a
standard
44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
256K x 16
ARRAY
A0
1041B–2
1024 x 4096
I/O0 – I/O7
OE
I/O8 – I/O15
CE
WE
BLE
BHE
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ
12
13
41
44
43
42
16
15
29
30
VCC
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A3
A4
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
VSS
I/O6
I/O4
I/O5
I/O7
A16
A15
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A14
A13
A12
A11
1041B–1
A9
A10
NC
TSOP II
Selection Guide
7C1041B-12
7C1041B-15
7C1041B-17
7C1041B-20
7C1041B-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Com’l
200
190
180
170
160
Ind’l
220
210
200
190
180
Maximum CMOS Standby Current
(mA)
Com’l
3
3
3
3
3
Com’l
L-
0.5
0.5
0.5
0.5
Ind’l
-
6
6
6
6
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