CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Document #: 38-06010 Rev. *A
Page 2 of 17
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty-7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65m
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
CY7C42X1V-15
CY7C42X1V-25
CY7C42X1V-35
Unit
Maximum Frequency
66.7
40
28.6
MHz
Maximum Access Time
11
15
20
ns
Minimum Cycle Time
15
25
35
ns
Minimum Data or Enable Set-up
4
6
7
ns
Minimum Data or Enable Hold
1
1
2
ns
Maximum Flag Delay
10
15
20
ns
Active Power Supply Current
Commercial
20
20
20
mA
CY7C4421V
CY7C4201V
CY7C4211V
CY7C4221V
CY7C4231V
CY7C4241V
CY7C4251V
Density
64 x 9
256 x 9
512 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Load
I
REN1, REN2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
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