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CYM1464 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CYM1464
Description  512Kx8 Static RAM Module
Download  8 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYM1464 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CYM1464
Document #: 38-05272 Rev. **
Page 3 of 8
Switching Characteristics Over the Operating Range[3]
Parameter
Description
1464-20
1464-22
1464-25
1464-30
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
20
22
25
30
ns
tAA
Address to Data Valid
20
22
25
30
ns
tOHA
Data Hold from Address Change
5
5
5
5
ns
tACS
CS LOW to Data Valid
20222530
ns
tDOE
OE LOW to Data Valid
13
13
15
15
ns
tLZOE
OE LOW to Low Z
0
0
0
0
ns
tHZOE
OE HIGH to High Z
0
10010
0
10010
ns
tLZCS
CS LOW to Low Z
5
5
5
10
ns
tHZCS
CS HIGH to High Z[4]
015015
0
15020
ns
WRITE CYCLE[5]
tWC
Write Cycle Time
20
22
25
30
ns
tSCS
CS LOW to Write End
15172025
ns
tAW
Address Set-Up to Write End
15
15
20
25
ns
tHA
Address Hold from Write End
3
3
3
3
ns
tSA
Address Set-Up to Write Start
5
5
5
5
ns
tPWE
WE Pulse Width
15151520
ns
tSD
Data Set-Up to Write End
12
12
15
15
ns
tHD
Data Hold from Write End
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
0
ns
tHZWE
WE LOW to High Z[4]
15
15
15
15
ns
Switching Characteristics Over the Operating Range [3]
Parameter
Description
1464-35
1464-45
1464-55
Unit
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
35
45
55
ns
tAA
Address to Data Valid
35
45
55
ns
tOHA
Data Hold from Address Change
5
5
5
ns
tACS
CS LOW to Data Valid
35
45
55
ns
tDOE
OE LOW to Data Valid
20
25
30
ns
tLZOE
OE LOW to Low Z
0
0
0
ns
tHZOE
OE HIGH to High Z
0
15
0
15
0
15
ns
tLZCS
CS LOW to Low Z
10
10
10
ns
tHZCS
CS HIGH to High Z[4]
020
0
20
020
ns
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4.
tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
5.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.


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