PRELIMINARY
CY23S08
Document #: 38-07265 Rev. *D
Page 2 of 8
Spread Aware™
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
For more details on Spread Spectrum timing technology,
please see Cypress’s application note EMI Suppression
Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.
Notes:
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-ups on these inputs.
Table 1. Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Three-State
Three-State
PLL
Y
0
1
Driven
Three-State
PLL
N
1
0
Driven
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
Table 2. Available CY23S08 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY23S08–1
Bank A or Bank B
Reference
Reference
CY23S08–1H
Bank A or Bank B
Reference
Reference
CY23S08–2
Bank A
Reference
Reference/2
CY23S08–2H
Bank A
Reference
Reference/2
CY23S08–2
Bank B
2 X Reference
Reference
CY23S08–2H
Bank B
2 X Reference
Reference
CY23S08–3
Bank A
2 X Reference
Reference or Reference[1]
CY23S08–3
Bank B
4 X Reference
2 X Reference
CY23S08–4
Bank A or Bank B
2 X Reference
2 X Reference
Pin Description
Pin
Signal
Description
1REF[2]
Input reference frequency, 5V tolerant input
2
CLKA1[3]
Clock output, Bank A
3
CLKA2[3]
Clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[3]
Clock output, Bank B
7
CLKB2[3]
Clock output, Bank B
8S2[4]
Select input, bit 2
9S1[4]
Select input, bit 1
10
CLKB3[3]
Clock output, Bank B
11
CLKB4[3]
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[3]
Clock output, Bank A
15
CLKA4[3]
Clock output, Bank A
16
FBK
PLL feedback input