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CY28346 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY28346
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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CY28346
Document #: 38-07331 Rev. *B
Page 4 of 20
Byte 2: PCI Clock Control Register (all bits are Read and Write functional)
Bit
@Pup
Pin#
Description
7
0
53
REF Output Control. 0 = high strength, 1 = low strength.
6
1
18
PCI6 Output Control. 1 = enabled, 0 = forced LOW.
5
1
17
PCI5 Output Control. 1 = enabled, 0 = forced LOW.
4
1
16
PCI4 Output Control. 1 = enabled, 0 = forced LOW.
3
1
13
PCI3 Output Control. 1 = enabled, 0 = forced LOW.
2
1
12
PCI2 Output Control. 1 = enabled, 0 = forced LOW.
1
1
11
PCI1 Output Control. 1 = enabled, 0 = forced LOW.
0
1
10
PCI0 Output Control. 1 = enabled, 0 = forced LOW.
Byte 3: PCI_F Clock and 48M Control Register (all bits are Read and Write functional)
Bit
@Pup
Pin#
Description
7
1
38
48MDOT Output Control. 1 = enabled, 0 = forced LOW.
6
1
39
48MUSB Output Control. 1 = enabled, 0 = forced LOW.
5
0
7
PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
4
0
6
PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
3
0
5
PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
2
1
7
PCI_F2 Output Control. 1 = running, 0 = forced LOW.
1
1
6
PCI_F1 Output Control. 1 = running, 0 = forced LOW.
0
1
5
PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register (all bits are Read and Write functional)
Bit
@Pup
Pin#
Description
7
0
SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
6
0
Reserved. Set = 0.
5
1
33
3V66_0 Output Enabled. 1 = enabled, 0 = disable.
4
1
35
3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.
3
1
24
3V66_5 Output Enable. 1 = enabled, 0 = disabled.
2
1
23
66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.
1
1
22
66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.
0
1
21
66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.
Byte 5: Clock Control Register (all bits are Read and Write functional)
Bit
@Pup
Pin#
Description
7
0
SS1 Spread Spectrum Control Bit.
6
1
SS0 Spread Spectrum Control Bit.
5
0
66IN to 66M delay Control MSB.
4
0
66IN to 66M delay Control LSB.
3
0
Reserved. Set = 0.
2
0
48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.
1
0
Reserved. Set = 0.
0
0
USB edge rate control. When set to 1, the edge is slowed by 15%.


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