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CY28346 Datasheet(PDF) 17 Page - Cypress Semiconductor

Part No. CY28346
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346 Datasheet(HTML) 17 Page - Cypress Semiconductor

 
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CY28346
Document #: 38-07331 Rev. *B
Page 17 of 20
TPZL/TPZH
Output Enable Delay
(All Outputs)
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
ns
10
TPZL/TPZH
Output disable delay (all
outputs)
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
ns
10
TSTABLE
All Clock Stabilization
from Power-up
33
3
3
ms
10
TSS
Stopclock Set-up Time
10.0
10.0
10.0
10.0
ns
27
TSH
Stopclock Hold Time
0
0
0
0
ns
27
TSU
Oscillator Start-up Time
X
X
X
X
ms
28
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Units
PCI Clocks
30
pF
3V66 (0,1)
30
pF
66B(0:2)
30
pF
48MUSB Clock
20
pF
48MDOT
10
pF
REF Clock
50
pF
Notes:
27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
28. When crystal meets minimum 40
Ω device series resistance specification.
29. Device is not affected, VTT_PWRGD# is ignored.
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_GD#
Sample Sels
Off
Off
On
On
State 1
(Note A)
Figure 16. VTT_PWRGD# Timing


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