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CY28346 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY28346
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346 Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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CY28346
Document #: 38-07331 Rev. *B
Page 5 of 20
Byte 6: Silicon Signature Register[4] (all bits are Read-only)
Bit
@Pup
Pin#
Description
7
0
Revision = 0001
60
50
41
3
0
Vendor Code = 0011
20
11
01
Byte 7: Reserved Register
Bit
@Pup
Pin#
Description
70
Reserved. Set = 0.
60
Reserved. Set = 0.
50
Reserved. Set = 0.
40
Reserved. Set = 0.
30
Reserved. Set = 0.
20
Reserved. Set = 0.
10
Reserved. Set = 0.
00
Reserved. Set = 0.
Byte 8: Dial-a-Frequency Control Register N
Bit
@Pup
Name
Description
7
0
Reserved. Set = 0.
6
0
N6, MSB
These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50
N5
40
N4
30
N3
20
N2
10
N3
00
N0, LSB
Byte 9: Dial-a-Frequency Control Register R
Bit
@Pup
Name
Description
7
0
Reserved. Set = 0.
6
0
R5, MSB
These bits are for programming the PLL’s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50
R4
40
R3
30
R2
20
R1
10
R0
00
DAF_ENB
R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
Note:
4.
When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.


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