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CY7C68000
PRELIMINARY
Document #: 38-08016 Rev. *E
Page 10 of 14
9.2.2
HS/FS Interface Timing–30 MHz
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCVO
TCCO
DataIn
DataOut
Control_Out
Control_In
CLK
TCDO
TVSU_MIN
TVH_MIN
Figure 9-2. 30-MHz Timing Interface Timing Constraints
Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
TCSU_MIN
Minimum set-up time for TXValid
20
ns
TCH_MIN
Minimum hold time for TXValid
1
ns
TDSU_MIN
Minimum set-up time for Data (Transmit direction)
20
ns
TDH_MIN
Minimum hold time for Data (Transmit direction)
1
ns
TCCO
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
120
ns
TCDO
Clock to Data out time (Receive direction)
1
20
ns
TVSU_MIN
Minimum set-up time for ValidH (transmit Direction)
20
ns
TVH_MIN
Minimum hold time for ValidH (Transmit direction)
1
ns
TCVO
Clock to ValidH out time (Receive direction)
1
20
ns
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