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CY22150 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY22150
Description  One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY22150 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY22150
Document #: 38-07104 Rev. *F
Page 3 of 13
Default Start-up Condition for the CY22150
The default (programmed) condition of the device is generally
set by the distributor who programs the device using a
customer-specific JEDEC file produced by CyClocksRT
.
Parts shipped from the factory are blank and unprogrammed.
In this condition, all bits are set to 0, all outputs are
three-stated, and the crystal oscillator circuit is active.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages,
it may be easier to use CyClocksRT to produce the required
register setting file.
The serial interface address of the CY22150 is 69H. Should
there be a conflict with any other devices in your system, this
can also be changed using CyClocksRT.
Frequency Calculations and Register Defini-
tions Using the Serial Programming Interface
The CY22150 provides an industry standard serial interface
for volatile, in-system programming of unique frequencies and
options. Serial programming and reprogramming allows for
quick design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
The Serial Programming Interface (SPI) provides volatile
programming, i.e., when the target system is powered down,
the CY22150 reverts to its pre-SPI state, as defined above
(programmed or unprogrammed). When the system is
powered back up again, the SPI registers will need to be
reconfigured again.
All programmable registers in the CY22150 are addressed
with eight bits and contain eight bits of data. The CY22150 is
a slave device with an address of 1101001 (69H).
Table 1 lists the SPI registers and their definitions. Specific
register definitions and their allowable values are listed below.
Reference Frequency
The REF can be a crystal or a driven frequency. For crystals,
the frequency range must be between 8 MHz and 30 MHz. For
a driven frequency, the frequency range must be between
1 MHz and 133 MHz.
Using a Crystal as the Reference Input
The input crystal oscillator of the CY22150 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a REF source. The input oscillator has program-
mable gain, allowing for maximum compatibility with a
reference crystal, regardless of manufacturer, process, perfor-
mance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to Table 2. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
(Q+2)
VCO
(2(PB+4)+PO)
/2
/3
/2
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[45H,46H]
REF
PFD
Divider Bank 1
[45H]
DIV1SRC [OCH]
/4
DIV2SRC [47H]
Divider Bank 2
DIV1N [OCH]
DIV2N [47H]
/DIV1N
1
0
1
0
[42H]
[40H], [41H], [42H]
/DIV2N
Qtotal
Ptotal
CLKOE [09H]
Figure 1. Basic Block Diagram of CY22150 PLL


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