CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Document #: 38-06010 Rev. *A
Page 5 of 17
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42X1Vs. Any
word
width
can
be
attained
by
adding
additional
CY7C42X1Vs.
When the CY7C42X1V is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Notes:
2.
n = Empty Offset (n=7 default value).
3.
m = Full Offset (m=7 default value).
Table 2. Status Flags
Number of Words in FIFO
FF
PAF
PAE
EF
CY7C4421V
CY7C4201V
CY7C4211V
000
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
HH
L
H
(n+1) to 32
(n+1) to 128
(n+1) to 256
H
H
H
H
33 to (64
−(m+1))
129 to (256
−(m+1))
257 to (512
−(m+1))
H
H
H
H
(64
−m)[3] to 63
(256
−m)[3] to 255
(512
−m)[3] to 511
H
L
H
H
64
256
512
L
L
H
H
Number of Words in FIFO
FF
PAF
PAE
EF
CY7C4221V
CY7C4231V
CY7C4241V
CY7C4251V
0
000
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
1 to n[2]
HH
L
H
(n+1) to 512
(n+1) to 1024
(n+1) to 2048
(n+1) to 4096
H
H
H
H
513 to (1024
−(m+1)) 1025 to (2048 −(m+1)) 2049 to (4096 −(m+1)) 4097 to (8192 −(m+1))
H
H
H
H
(1024
−m)[3] to 1023
(2048
−m)[3] to 2047
(4096
−m)[3] to 4095
(8192
−m)[3] to 8191
H
L
H
H
1024
2048
4096
8192
L
L
H
H
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