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CY7C197
Document #: 38-05049 Rev. **
Page 4 of 10
Switching Characteristics Over the Operating Range[6]
Parameter
Description
7C197-12
7C197-15
7C197-20
7C197-25
7C197-35
7C197-45
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
35
45
ns
tAA
Address to
Data Valid
12
15
20
25
35
45
ns
tOHA
Output Hold from
Address Change
3
3
3
3
3
3
ns
tACE
CE LOW to
Data Valid
12
15
20
25
35
45
ns
tLZCE
CE LOW to
Low Z[7]
3
3
3
3
3
3
ns
tHZCE
CE HIGH to
High Z[7, 8]
5
7
0
9
0
11
0
15
0
15
ns
tPU
CE LOW to
Power-Up
0
0
0
0
0
0
ns
tPD
CE HIGH to
Power-Down
12
15
20
20
25
30
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
12
15
20
25
35
45
ns
tSCE
CE LOW to
Write End
9
10
15
20
30
40
ns
tAW
Address Set-Up to
Write End
9
10
15
20
30
40
ns
tHA
Address Hold from
Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
20
25
30
ns
tSD
Data Set-Up to
Write End
8
9
10
15
17
20
ns
tHD
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
Low Z[7]
2
2
3
3
3
3
ns
tHZWE
WE LOW to
High Z[7,8]
7
7
0
10
0
11
0
15
0
15
ns
Notes:
6.
Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7.
At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
8.
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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