SI5380_16 datasheet(42/53 Pages) SILABS

Part #	SI5380

Description	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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Manufacturer	SILABS [Silicon Laboratories]

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Table 9.1. Pin Descriptions

Pin Name

Pin Number

Pin Type1

Function

XA

8

I

Crystal Input. Input pin for external crystal (XTAL). Alterna-

tively these pins can be driven with an external reference

clock (REFCLK). An internal register bit selects XTAL or

REFCLK mode. Default is XTAL mode. Single-ended inputs

must be connected to the XA pin, with the XB pin appropri-

ately terminated.

XB

9

I

X1

7

I

XTAL Shield. Connect these pins directly to the crystal

ground pins. Both the X1/X2 pins and Crystal ground pins

should be separated from the PCB ground plane. Refer to

the Reference Manual for layout guidelines.

X2

10

I

IN0

63

I

Clock Inputs. These pins accept an input clock for syn-

chronizing the device. They support both differential and

single-ended clock signals. Refer to 3.3.1 Input Configura-

tion and Terminations for input termination options. These

pins are high-impedance and must be terminated externally,

when being used. The negative side of the differential input

must be ac-grounded when accepting a single-ended clock.

Unused inputs may be left unconnected.

IN0b

64

I

IN1

1

I

IN1b

2

I

IN2

14

I

IN2b

15

I

IN3/FB_IN

61

I

Clock Input 3/External Feedback Input.

By default, these pins are used as the 4th clock input (IN3/

IN3b). They can also be used as the external feedback in-

put (FB_IN/FB_INb) for the optional zero delay mode. See

section 5.3.6 for details on the optional zero delay mode.

IN3b/FB_INb

62

I

Outputs

Si5380 Rev D Data Sheet

Pin Description

silabs.com | Smart. Connected. Energy-friendly.

Rev. 1.0 | 41

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