Si5347A-D-GM datasheet(9/55 Pages) SILABS

Part #	Si5347A-D-GM

Description	Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Download	55 Pages

Scroll/Zoom	100%

Manufacturer	SILABS [Silicon Laboratories]

Direct Link	http://www.silabs.com

Logo

9 / 55 page

3.6.4 Input Configuration and Terminations

Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown

in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be dc-cou-

pled. Unused inputs can be disabled and left unconnected when not in use.

Standard AC-coupled Single-ended

100

Standard AC-coupled Differential LVPECL

3.3 V, 2.5 V

LVPECL

INx

INxb

INx

INxb

50

Si5347/46

3.3 V, 2.5 V, 1.8 V

LVCMOS

Pulsed CMOS

Standard

Pulsed CMOS

Pulsed CMOS DC-coupled Single-ended

3.3 V, 2.5 V, 1.8 V

LVCMOS

INx

INxb

Pulsed CMOS

Standard

Si5347/46

50

R

2

R1

VDD R1 (Ohm) R2 (Ohm)

1.8V

324

665

2.5V

511

475

3.3V

634

365

Resistor values for

fIN_PULSED < 1 MHz

50

100

Standard AC-coupled Differential LVDS

INx

INxb

3.3 V, 2.5 V

LVDS or CML

50

Si5347/46

Pulsed CMOS

Standard

Figure 3.5. Termination of Differential and LVCMOS Input Signals

3.6.5 Hitless Input Switching

Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that

have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that

they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,

the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-

ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching

feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL

basis.

Si5347/46 Rev D Data Sheet

Functional Description

silabs.com | Smart. Connected. Energy-friendly.

Rev. 1.0 | 8

Similar Part No. - Si5347A-D-GM

Manufacturer	Part #	Datasheet	Description
Skyworks Solutions Inc.	SI5347A-D-GM	879Kb / 56P	Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators Rev. 1.1

More results

Similar Description - Si5347A-D-GM

Manufacturer	Part #	Datasheet	Description
Silicon Laboratories	SI5347	2Mb / 59P	DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS
Skyworks Solutions Inc.	SI5347	879Kb / 56P	Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators Rev. 1.1
Skyworks Solutions Inc.	SI5397	1Mb / 60P	Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators Rev. 1.2
Silicon Laboratories	SI5341	2Mb / 56P	LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR
	SI5345	1Mb / 60P	10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
	SI5345	1Mb / 62P	10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER
Skyworks Solutions Inc.	SI5391	1Mb / 45P	Ultra Low-Jitter, 12-Output, Any-Frequency, Any-Output Clock Generator Rev. 0.7
	SI5345	976Kb / 58P	10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier Rev. 1.2
	SI5334	1Mb / 37P	PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR Rev. 1.3
	SI5341	1Mb / 49P	Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator Rev. 1.1

More results

Si5347A-D-GM Datasheet(PDF) 9 Page - Silicon Laboratories

Si5347A-D-GM Datasheet(HTML) 9 Page - Silicon Laboratories

Similar Part No. - Si5347A-D-GM

Similar Description - Si5347A-D-GM

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL