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SI5348 Datasheet(PDF) 28 Page - Silicon Laboratories |
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SI5348 Datasheet(HTML) 28 Page - Silicon Laboratories |
28 / 54 page Table 5.4. Control Input Pin Specifications Parameter Symbol Test Condition Min Typ Max Unit Si5348 Control Input Pins (I2C_SEL, A0/CSb, A1/SDO, SDA/SDIO, SCLK, RSTb, OE0b, OE1b, OE2b, FINC) Input Voltage VIL — — 0.3 × VDDIO1 V VIH 0.7 × VDDIO1 — — V Input Capacitance CIN — 2 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW RSTb, FINC 100 — — ns Update Rate FUR FINC — — 1 MHz Si5348 Control Input Pin (FDEC) Input Voltage VIL — — 0.3 × VDDS V VIH 0.7 × VDDS — — V Input Capacitance CIN — 2 — pF Minimum Pulse Width PW FDEC 100 — — ns Update Rate FUR FDEC — — 1 MHz Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Table 5.5. Differential Clock Output Specifications Parameter Symbol Test Condition Min Typ Max Unit Output Frequency fOUT 0.0001 — 712.5 MHz fOUT1Hz 1 PPS signal only available on Output 6 1 Hz Duty Cycle DC fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 712.5 MHz 45 — 55 % Output-Output Skew Using Same DSPLL TSKS Outputs on same DSPLL (Measured at 712.5 MHz) — — 65 ps OUT-OUTb Skew TSK_OUT Measured from the positive to negative output pins — 0 50 ps Output Voltage Amplitude1 VOUT VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 430 510 mVpp_se LVPECL 640 750 900 Si5348 Rev D Data Sheet Electrical Specifications silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 27 |
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