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DS90CR483VJD Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS90CR483VJD Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 17 page  Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVDS RECEIVER DC SPECIFICATIONS V TH Differential Input High Threshold V CM = +1.2V +100 mV V TL Differential Input Low Threshold −100 mV I IN Input Current V IN = +2.4V, VCC = 3.6V ±10 µA V IN = 0V, VCC = 3.6V ±10 µA TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case R L = 100Ω,CL = 5 pF, Worst Case Pattern ( Figures 1, 2) f = 33 MHz 91.4 140 mA f = 66 MHz 106 160 mA f = 112 MHz 155 190 mA ICCTZ Transmitter Supply Current Power Down PD = Low 550 µA Driver Outputs in TRI-STATE under Powerdown Mode RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case C L = 8 pF, Worst Case Pattern ( Figures 1, 3) f = 33 MHz 125 150 mA f = 66 MHz 215 250 mA f = 112 MHz 350 380 mA ICCRZ Receiver Supply Current Power Down PD = LowReceiver Outputs stay low during Power down mode. 20 100 µA Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time ( Figure 4) 1.0 2.0 3.0 ns TCIP TxCLK IN Period ( Figure 5) 8.928 T 30.3 ns TCIH TxCLK in High Time ( Figure 5) 0.35T 0.5T 0.65T ns TCIL TxCLK in Low Time ( Figure 5) 0.35T 0.5T 0.65T ns TXIT TxIN Transition Time 1.5 6.0 ns Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time, ( Figure 2), PRE = 0.75V (disabled) 0.14 0.7 ns LVDS Low-to-High Transition Time, ( Figure 2), PRE = Vcc (max) 0.11 0.6 ns LHLT LVDS High-to-Low Transition Time, ( Figure 2), PRE = 0.75V (disabled) 0.16 0.8 ns LVDS High-to-Low Transition Time, ( Figure 2), PRE = Vcc (max) 0.11 0.7 ns TBIT Transmitter Bit Width 1/7 TCIP ns TCCS TxOUT Channel to Channel Skew 100 ps TSTC TxIN Setup to TxCLK IN, ( Figure 5) 2.5 ns THTC TxIN Hold to TxCLK IN, ( Figure 5)0 ns TPDL Transmitter Propagation Delay - Latency, ( Figure 7) 1.5(TCIP)+3.72 1.5(TCIP)+4.4 1.5(TCIP)+6.24 ns TPLLS Transmitter Phase Lock Loop Set, ( Figure 9)10 ms TPDD Transmitter Powerdown Delay, ( Figure 11) 100 ns www.national.com 4 |
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