3

SP8602/4

OPERATING NOTES

1. The clock inputs (pins 1 and 2) can be driven single ended or

differentially and should be capacitively coupled to the signal

source. The input signal path is completed by connecting a

capacitor from the internal bias decoupling, pin 3, to ground.

2. In the absence of a signal the device will self-oscillate. If this is

undesirable, it may be prevented by connecting a 15k

Ω resistor

by approximately 100mV.

3. The circuit will operate down to DC but slew rate must be better

than 100V/

µs.

4. The outputs are compatible with ECLII. There is an internal load

of 4k

Ω on each output. The outputs can be interfaced to ECL10K

by the addition of 1·5k

Ωpulldown resistors from the outputs to V

EE

to increase output voltage swing.

5. Input impedance is a function of frequency, See Fig. 4.

6. All components should be suitable for the frequency in use.

Fig. 5 Test circuit

Fig. 6 Typical application showing interfacing

DUT

450

450

10n

10n

TO SAMPLING

SCOPE

5

6

7

8

1

2

1n

1n

FROM GENERATOR

INPUT 1

TO SAMPLING

SCOPE

1n

33

33

20

1n

33

20

33

1n

33

20

3

TO SAMPLING

SCOPE

FROM GENERATOR

INPUT 2

3·5k

3·5k

7

6

4k

4k

8

440

1

2

5

BIAS

ECL OUTPUT

1·5k

15k

1n

1n

1n

1·5k

INPUT

440

DIVIDE BY

2