OSD PROCESSOR FOR MONITORS

S5D2501F

7

FUNCTIONAL DESCRIPTIONS

Data Transmission to the S5D2501F

line are shown in Figure 4. As shown in Figure 4, after the starting pulse, the slave address with R/W* bit and an

acknowledge are transmitted in sequence, an internal register address of the S5D2501F is followed. The first 8-bit

byte is the upper 8bits of the register address. The lower 8bits of the register address are followed after the second

acknowledge. There is a data transmission format and are two address bit patterns in the S5D2501F as following.

The slave address of the S5D2501F is BAH(in hexadecimal).

Data Transmission Format

Row Address -> Column Address -> Data Byte N -> Data Byte N+1 -> Data Byte N+2 -> ....

Address Bit Pattern for Display Registers Data

(a) Row Address Bit Pattern

R3 - R0: Valid Data for Row Address

(b) Column Address Bit Pattern

C4 - C0: Valid Data for Column Address

After addressing, data bytes are followed as the above data transmission format. The Figure 4 describes the data

Figure 4. (a) SDA line and SCL line (Write Operation)

Figure 4. (b)SDA line and SCL line (Read Operation)

A15

A14

A13

A12

A11

A10

A9

A8

X

X

X

X

R3

R2

R1

R0

A7

A6

A5

A4

A3

A2

A1

A0

X

X

X

C4C3

C2C1

C0

D

D

D

D

EE

E

E

E

D

D

D

D

E

C

C

E

E

C

C

D

D

C

C

D

D

D

D

EE

E

E

E

D

D

D

D

E

CC

E

E

CC

EE