Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

RCOP

RxCLK OUT Period (

Figure 7 )

15

T

50

ns

RCOH

RxCLK OUT High Time (

Figure 7 )f = 40 MHz

6

ns

f = 66 MHz

4.3

5

ns

RCOL

RxCLK OUT Low Time (

Figure 7 )f = 40 MHz

10.5

ns

f = 66 MHz

7.0

9

ns

RSRC

RxOUT Setup to RxCLK OUT (

Figure 7 )f = 40 MHz

4.5

ns

f = 66 MHz

2.5

4.2

ns

RHRC

RxOUT Hold to RxCLK OUT (

Figure 7 )f = 40 MHz

6.5

ns

f = 66 MHz

4

5.2

ns

RCCD

6.4

10.7

ns

RPLLS

Receiver Phase Lock Loop Set (

Figure 11 )10

ms

RPDD

Receiver Powerdown Delay (

Figure 15 )1

µs

Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)

and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.

RSKM

≥ cable skew (type, length) + source clock jitter (cycle to cycle)

AC Timing Diagrams

DS012888-2

FIGURE 1. “Worst Case” Test Pattern

DS012888-3

DS012888-4

FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times

DS012888-5

DS012888-6

FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times

5

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PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5

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