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MN1959041 Datasheet(PDF) 12 Page - Panasonic Semiconductor

Part No. MN1959041
Description  COMMERCIAL MPEG-4 VIDEO CODEC IC FOR W-CDMA MOBILE VISUAL TERMINALS
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Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
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MN1959041 Datasheet(HTML) 12 Page - Panasonic Semiconductor

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MN1959041
12
SDM00008AEM
Pin
I/O
Description
VMCK
I
PLL
MMP-V operation reference clock (input to the PLL)
76.8 KHz
NPLLEN
I
MMP1 internal operating clock selection
Low
PLLEN
I
Selection of the clock input the MMP1 internal divide-by-two circuit
High
NPLLRST
I
MMP-V internal PLL reset
High
VCOI
I
VCO analog voltage input
AVDD
PLL power supply:
+2.9 V
2.9 V
AVSS
PLL ground
AVSS
CFO
Power supply
Test pin
High
PSCMR
I
Test pin
High
VDDH
Power supply:
+2.9 V
2.9 V
VDD
Power supply:
+1.8 V
1.8 V
VSS
Ground
DGND
VDDDRAMH
DRAM power supply:
+3.3 V
3.3 V
VDDDRAM
DRAM power supply:
+1.8 V
1.8 V
VSSDRAM
DRAM ground
GND
PVBBDRAM
P detection substrate power supply monitor output
PVBPDRAM
P detection test bit line precharge power supply monitor output
s Pin Descriptions (continued)
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = 0 V
Parameter
Symbol
Rating
Unit
External supply voltage *
VDD
− 0.3 to +4.6
V
Internal supply voltage *
VDDI
− 0.3 to +2.5
V
Input pin voltage
VI
− 0.3 to V
DD + 0.3 (Upper limit: 4.6)
V
Output pin voltage
VO
− 0.3 to V
DD + 0.3 (Upper limit: 4.6)
V
Output current (Type HL4 pins)
IO
±20
mA
Power supply input current
IV
±70 (Per pin)
mA
Power dissipation
PD
1.77
mW
Operating temperature
Topr
−20 to +70
°C
Storage temperature
Tstg
−55 to +150
°C
Note) 1. *: When one of VDD and VDDI is off and the other on, through currents flow and the outputs will be undefined. There are
no stipulation on the power on and power off sequences. The power supply levels should be applied as close to
simultaneously as possible. However, this does no apply when CFO is controlled.
2. Type HL4 pins: CIFRQ, CAMCK, VFLG, I2CSD, LRDO[0] to LRDO[5], LGDO[0] to LGDO[5], LBDO[0] to LBDO[5],
NLVSYNCO, NLHSYNCO, LVVALIDO, LHVALIDO, LVCKO, PO[0], PO[1], NVRESRTO, VD[0] to
VD[15], VPIO[0] to VPIO[3], VST[0] to VST[2], VTCK, VTDI, VTDO, VTRWEN, TEST[0] to TEST[8]
3. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed.
Functional operation is not guaranteed over the complete span of these ranges.
4. All of the VDD and VSS pins must be connected directly to their corresponding power supply and ground levels.
Normal
usage


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