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MN1959041 Datasheet(PDF) 6 Page - Panasonic Semiconductor

Part No. MN1959041
Description  COMMERCIAL MPEG-4 VIDEO CODEC IC FOR W-CDMA MOBILE VISUAL TERMINALS
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Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
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MN1959041 Datasheet(HTML) 6 Page - Panasonic Semiconductor

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MN1959041
6
SDM00008AEM
s Functional Description (continued)
4. VCE (Video Coded Engine) Block (continued)
Table 3. Decoder Engines
The CAD, PADDING, and COMPOSITE items in the above table are core profile engines.
The engines in the VCE block are classified into type A and type B engines. Type A engines operate independently
of the MP block, and type B engines operate in conjunction with the MP block.
5. MIF (Memory Interface) Block
The MIF block arbitrates and controls DMA transfers between the MP, HIF, and VIF functional blocks. The fol-
lowing are the main types of DMA transfers provided.
• Data transfers with the MP DM (Data Memory). These are used for functions such as motion detection and com-
pensation.
• Data transfers with the HIF HM (HIF Memory). These are used for bit stream data.
• Image data I/O transfers with VIF performed at fixed periods.
Requests for DMA transfers other than video I/O are issued with priorities assigned from the MP. Although VIF
DMA transfers are performed with the highest priority (level 0), the transfer priority for other DMA transfers can be
specified. Table 4 lists the types of priority level.
Table 4. Priority Level Types
The MIF supports the four addressing modes listed below.
1) P
+
: Consecutive access
2) Sag
+ : Matrix access
3) RP
+
: Ring buffer access
4) RP
+DF : Ring buffer access with start address offset (every transfer)
MN1959041 provides two large-capacity DRAMs; working memory and frame memory. Working memory is
mainly used for image compression and expansion, and frame memory is mainly used as the frame buffer used for
VIF image output. Working memory is 16 Mbits of DRAM formed from four 4 Mbit DRAMs. Frame memory
consists of a video buffer and a graphics buffer, each of which formed from a single 2 Mbit DRAM for a total of 2
DRAM chip. The operation frequency used is 53.76 MHz. Table 5 lists the internal DRAM structures and details of
these memories.
Engine
Function
Type
MEH
Half pel generation
A
IDCT
One-dimensional IDCT calculation
B
VLD
Variable-length decoding
A
PNR
Blocking noise elimination
B
PADDING
Horizontal/vertical, expanded, and fixed-value padding
A
CAD
Shape information decoding
A
COMPOSITE
Image composition
B
THROUGH
Data through (Data is output without processing)
B
Level
Priority
Usage
Level 0
High
Only used for image I/O
Level 1
Programmable
Level 2
Level 3
Low


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