Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MN1959041 Datasheet(PDF) 5 Page - Panasonic Semiconductor

Part No. MN1959041
Description  COMMERCIAL MPEG-4 VIDEO CODEC IC FOR W-CDMA MOBILE VISUAL TERMINALS
Download  23 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
Logo 

MN1959041 Datasheet(HTML) 5 Page - Panasonic Semiconductor

 
Zoom Inzoom in Zoom Outzoom out
 5 / 23 page
background image
MN1959041
5
SDM00008AEM
s Functional Description (continued)
2. IRC (Interrupt Controller) Block (continued)
Table 1. Interrupt Types
3. HIF (Host Interface) Block
The HIF block performs the data transfers between MN1959041 and an external CPU. The IC and the CPU are
connected by a 16-bit data bus. During these transfers, the CPU must set, in advance, the bus mode, which determines
the physical usage of the data bus. The CPU must set up 16-bit bus mode for transfers with the IC, but can use 8-bit
or 16-bit access for other purposes. For example, the CPU can use 8-bit access for bit stream data, and use 16-bit
access for all other data transfers.
A total of 32 signal lines are required for to the host memory (HM), and for write operations, the IC uses two write
enable lines to distinguish between 8-bit and 16-bit access. For read access, the IC always operates in 16-bit output mode
in response to the read enable signal. (The CPU must distinguish between the 16 bits of valid data and 8 bits of valid
data cases.)
4. VCE (Video Coded Engine) Block
MN1959041 includes a built-in VCE that executes video codec operations at high speeds. In particular, it includes
the following circuits.
• Motion detection circuits (MEF, MEH)
• Discrete cosine transformation/inverse discrete cosine transformation circuits (DCT/IDCT)
• Variable-length encoding and decoding circuits (VLC/VLD)
• Blocking noise elimination circuit (PNR)
• Shape information decoding circuit (CAD)
• Pixel supplementing circuit (PADDING)
• Image synthesis circuit (COMPOSITE)
The tables below shows the special-purpose circuits (engines) that form the VCE classified as encoder engine or
decoder engine.
Table 2. Encoder Engines
Priority level
Masking
Interrupt
1
High
Nonmaskable
Watchdog timer interrupt
2
Nonmaskable
External pin nonmaskable interrupt
3
Maskable
Stack exception (stack overflow)
Maskable
Stack exception (stack underflow)
Maskable
Software interrupt
Maskable
Interrupt request No. 0
·
··
Low
Interrupt request No. 12
Engine
Function
Type
MEF
Full pel motion detection
A
MEH
Half pel motion detection
A
VLC
Variable-length coding
A
DCT/IDCT
One-dimensional DCT/IDCT calculation
B


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn