RF OUTPUT STAGE

MOTOROLA

MC33493 Technical Data

3

Table 1: Band selection and associated divider ratios

An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the

RF output stage is disabled.

RF OUTPUT STAGE

The output stage is a single ended square wave switched current source. Harmonics are present in the output

current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical

application demonstrates compliance to ETSI standard.

and current consumption.

MODULATION

A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation

is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output

stage state:

DATA=0

DATA=1

If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This

modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the

external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel.

The logic level applied on pin DATA controls the state of this internal switch:

DATA=0

DATA=1

DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty

cycle cannot exceed

±1 reference period (±75ns for a 13.56MHz crystal).

This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation

multiplied by the PLL Divider Ratio (see table 1).

BAND Input

Level

Frequency

Band (MHz)

PLL Divider

Ratio

Crystal Oscillator

Frequency (MHz)

High

315

32

9.84

434

13.56

Low

868

64

Freescale Semiconductor, Inc.

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