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DS90CF584MTD Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DS90CF584MTD Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 12 page Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time ( Figure 4) 2.5 4.0 ns CHLT CMOS/TTL High-to-Low Transition Time ( Figure 4) 2.0 3.5 ns RCOP RxCLK OUT Period 15 T 50 ns RCOH RxCLK OUT High Time f = 65 MHz 7.8 9 ns RCOL RxCLK OUT Low Time f = 65 MHz 3.8 5 ns RSRC RxOUT Setup to RxCLK OUT f = 65 MHz 2.5 4.2 ns RHRC RxOUT Hold to RxCLK OUT f = 65 MHz 4.0 5.2 ns RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, V CC = 5.0V 6.4 10.7 ns ( Figure 10) RPLLS Receiver Phase Lock Loop Set ( Figure 12)10 ms RSKM RxIN Skew Margin (Note 6) ( Figure 14)V CC = 5V, TA =25˚C 600 ps RPDD Receiver Powerdown ( Figure 17)1 µs Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter. RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle) AC Timing Diagrams DS012616-3 FIGURE 1. “Worst Case” Test Pattern www.national.com 5 |
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