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PT6886 Datasheet(PDF) 4 Page - Texas Instruments |
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PT6886 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 10 page Application Notes For technical support and more information, see inside back cover or visit www.ti.com PT6880 Series Table 1-1: Input/Output Capacitors Notes: (1) N/R –Not recommended. The voltage rating does not meet the minimum operating limits. (2) A fused input bus is recommended when tantalum capacitors are used on the output bus. Capacitor Recommendations for the PT6880 Regulator Series Input Capacitor: The required input capacitor is determined by a 1.2Arms minimum ripple current rating and 560µF capacitance value. The ripple current rating and <120m Ω equivalent series resistance (ESR) are the major considerations, along with temperature, when designing with different types of capacitors. Tantalum/Os-Con® capacitors are not recommended due to a minimum voltage rating of 2 × (the maximum DC voltage + AC ripple). This is necessary to improve the reliability of these capacitors in high bus applications. Output Capacitors: The ESR specification of the output capacitor should be at least 50m Ω. Electrolytic capacitors have marginal ripple performance at frequencies greater than 400kHz but excellent low frequency transient response. Above the ripple frequency ceramic capacitors are necessary to improve the transient response and reduce any high- frequency noise components apparent during higher current excursions. Electrolytic capacitors with appropriate ESR values are identified in Table 1-1. In low-temperature applications (<0°C), a higher capacitance with lower ESR will improve performance. Os-Con® and ultra low ESR type capacitors are not recom- mended on the output bus as they degrade regulator stability. Tantalum Capacitors (For Vout <5.1V) Tantalum type capacitors can be used on the output bus for output voltages less than 5.1V. Voltages higher than this will exceed the capacitor’s published surge voltage limits. If tantalum capacitors are located on the output bus, an appropriate fuse with I2t current derating is recommended along with an external clamp component. An Output Over-voltage Clamp (OOVC) will fault the output fuse protecting the capacitors in event of an over-voltage condi- tion. The OOVC can be a simple zener high power di- ode, 3-5W, located on the load side of the output bus. The zener diode should be rated to 1.3 times the normal out- put voltage. Capacitor Table Table 1-1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current (rms) ratings. The number of capacitors required at both the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The RMS ripple current rating and ESR (Equivalent Series Resistance at 100kHz) are critical parameters necessary to insure both optimum regulator performance and long capacitor life. / r o d n e V r o t i c a p a C s e i r e S s c i t s i r e t c a r a h C r o t i c a p a Cy t i t n a u Q g n i k r o W e g a t l o V ) F µ ( e u l a Vt n e l a v i u q E ) R S E ( e c n a t s i s e R s e i r e S m u m i x a M C ° 5 0 1 e l p p i R ) s m r I ( t n e r r u C l a c i s y h P ) m m ( e z i S t u p n I s u B t u p t u O s u B r e b m u N t r a P r o d n e V c i n o s a n a P ) l a i d a R ( C F ) g t M e c a f r u S ( K F / C F V 0 5 V 0 5 V 0 5 V 3 6 V 5 3 V 0 5 0 6 5 0 9 3 0 9 3 0 8 6 0 3 3 0 0 0 1 8 6 0 . 0 Ω 0 8 0 . 0 Ω 0 8 0 . 0 Ω 0 8 0 0 Ω 0 8 0 . 0 Ω 3 7 0 . 0 Ω A m 0 0 9 1 A m 0 1 6 1 A m 0 1 6 1 A m 0 9 6 1 A m 0 5 8 A m 0 1 6 1 8 1 × 5 1 5 1 x 6 1 6 1 × 5 1 8 1 × 5 . 6 1 0 1 × 2 . 0 1 6 1 × 5 . 6 1 1 2 2 1 R / N ) 1 ( 1 1 1 1 1 1 1 1 6 5 H 1 C F U E E S 1 9 3 H 1 C F U E E S 1 9 3 H 1 C F U E E M 1 8 6 J 1 K F V E E P 1 3 3 V 1 K F V E E M 2 0 1 H 1 K F V E E n o c - i m e h C d e t i n U s e i r e S V X L / Z X L ) g t M e c a f r u S ( Y V M V 0 5 V 5 3 V 5 3 0 8 6 0 3 3 0 2 2 8 4 0 . 0 Ω 8 6 0 . 0 Ω 0 5 1 . 0 Ω A m 0 4 8 1 A m 0 5 0 1 A m 0 7 6 6 1 × 0 2 0 1 × 6 1 0 1 × 3 . 0 1 1 R / N ) 1 ( R / N ) 1 ( 1 1 2 L L 0 2 X 6 1 M 1 8 6 B V 0 5 Z X L L L 6 1 X 0 1 M 1 3 3 B V 5 3 V X L P T 0 1 X 0 1 M 1 1 2 2 C V 5 3 Y V M n o c i h c i N s e i r e S M P V 0 5 V 3 6 V 0 5 0 6 5 0 6 5 0 3 3 4 4 0 . 0 Ω 9 3 0 . 0 Ω 0 6 0 . 0 Ω A m 0 5 5 1 A m 0 0 4 1 A m 0 1 2 1 6 1 × 0 2 8 1 × 0 2 6 1 × 5 1 1 1 2 1 1 1 6 H H M 1 6 5 H 1 M P U 6 H H M 1 6 5 J 1 M P U 6 H H M 1 3 3 H 1 M P U m u l a t n a T X V A ) t g t M e c a f r u S ( S P T V 0 1 V 0 1 0 3 3 0 3 3 0 1 . 0 Ω 6 0 . 0 Ω A m 0 0 5 2 > A m 0 0 0 3 > L 3 . 7 × W 7 . 5 × H 1 . 4 R / N ) 1 ( R / N ) 1 ( 1 1 0 0 1 0 R 0 1 0 M 7 3 3 E S P TV ( o ) V 1 . 5 < 0 6 0 0 R 0 1 0 M 7 3 3 V S P TV ( o ) V 1 . 5 < m u l a t n a T t e m e K ) 2 ( s e i r e S 5 9 4 T / 6 9 4 T (t n u o M e c a f r u S) V 0 1 V 0 1 0 2 2 0 2 2 0 0 5 . 0 Ω 0 7 0 . 0 Ω A m 0 0 5 A m 0 0 0 2 > W 3 . 4 × L 3 . 7 × H 0 . 4 R / N ) 1 ( R / N ) 1 ( 2 2 S A 0 1 0 M 7 2 2 X 6 9 4 TV ( o ) V 1 . 5 < S A 0 0 1 0 M 7 2 2 X 5 9 4 TV ( o ) V 1 . 5 < m u l a t n a T e u g a r p S ) 2 ( s e i r e S D 4 9 5 (t n u o M e c a f r u S) V 0 10 3 30 3 1 . 0 Ω A m 3 9 3 1L 2 . 7 × W 6 × H 1 . 4 R / N ) 1 ( 1T 2 R 0 1 0 0 X 7 3 3 D 5 9 5V ( o ) V 1 . 5 < |
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