Electronic Components Datasheet Search |
|
PLL1708DBQRG4 Datasheet(PDF) 3 Page - Texas Instruments |
|
|
PLL1708DBQRG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 25 page PLL1707 PLL1708 SLES065 – DECEMBER 2002 www.ti.com 3 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic input CMOS compatible VIH (1) Input logic level 0.7VDD 3.6 Vdc VIL (1) Input logic level 0.3 VDD Vdc IIH (1) Input logic current VIN = VDD 65 100 µA IIL (1) Input logic current VIN = 0 V ±10 µA Logic output CMOS VOH (2) Output logic level IOH = –4 mA VDD – 0.4 V Vdc VOL (2) Output logic level IOL = 4 mA 0.4 Vdc PLL1707 Standard fS 32 44.1 48 PLL1707 Double fS 64 88.2 96 Sampling frequency Half fS 16 22.05 24 kHz Sam ling frequency PLL1708 Standard fS 32 44.1 48 kHz PLL1708 Double fS 64 88.2 96 MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency 26.73 27 27.27 MHz VIH Input level(3) 0.7 VCC V VIL Input level(3) 0.3 VCC V IIH Input current(3) VIN = VCC ±10 µA IIL Input current(3) VIN = 0 V ±10 µA Output voltage (4) 3.5 Vp-p Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Duty cycle For crystal oscillation 45% 51% 55% Duty cycle For external clock 50% Clock jitter (5) 50 ps Power-up time (6) 0.5 1.5 ms PLL AC CHARACTERISTICS (SCKO0–SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed 33.8688 SCKO1 PLL1707 Selectable for 48 kHz 24.576 36.864 SCKO2 PLL1707 256 fS 8.192 12.288 24.576 SCKO3 Output system clock 384 fS 12.288 18.432 36.864 MHz SCKO0 Out ut system clock frequency Fixed 33.8688 MHz SCKO1 qy PLL1708 Selectable for 48 kHz 12.288 24.576 36.864 SCKO2 PLL1708 256 fS 4.096 12.288 24.576 SCKO3 384 fS 6.144 18.432 36.864 Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Output duty cycle 45 50 55 % (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode. |
Similar Part No. - PLL1708DBQRG4 |
|
Similar Description - PLL1708DBQRG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |