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PLL1700EG4 Datasheet(PDF) 10 Page - Texas Instruments |
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PLL1700EG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 15 page PLL1700 10 SBOS096A www.ti.com DATE REVISION PAGE SECTION DESCRIPTION — Entire Document Updated format to current standard look. Added note (1) to VIH and VIL. Added two rows to Input Logic Level for VIH and VIL with note (2). Added condition to Clock Duty Cycle row stating that C1 = C2 = 15pF. Changed "X2 should be connected" to "X2 must be connected." Added text regarding signal amplitude. Changed voltage from 2.0V to 1.2V. Changed voltage from 0.8V to 0.4V. Changed tXT1H min value from 15 to 10. 6 Sampling Group Select Added text regarding interval time. 8 Mode Register Added text regarding interval time. Deleted note (1) from C1 and C2. Changed note text from "tantalum" to "electrolytic" capacitor. Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 5/07 A 3 Electrical Characteristics 5 Master Clock and System Clock Output 5 Figure 5 9 Figure 10 |
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