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TPS61222MDCKTEP Datasheet(PDF) 2 Page - Texas Instruments

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Part # TPS61222MDCKTEP
Description  LOW INPUT VOLTAGE, 0.7-V BOOST CONVERTER WITH 5.5-A QUIESCENT CURRENT
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS61222MDCKTEP Datasheet(HTML) 2 Page - Texas Instruments

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TPS61222-EP
SLVSBI2 – SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE DEVICE OPTIONS(1)
PACKAGE
TJ
PACKAGE(2)
PART NUMBER
VID NUMBER
MARKING
–55°C to 125°C
SHL
6-Pin SC-70
TPS61222MDCKTEP
V62/12603-01XE
(1)
Contact the factory to check availability of other fixed output voltage versions.
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
VIN
Input voltage range on VIN, L, VOUT, EN, FB
–0.3 to 7.5
V
TJ
Operating junction temperature range
–55 to 145
°C
Tstg
Storage temperature range
–65 to 150
°C
Human Body Model (HBM)(2)
2
kV
ESD
Machine Model (MM)(2)
200
V
Charged Device Model (CDM)(2)
1.5
kV
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS61222
THERMAL METRIC(1)
DCK
UNITS
6 PINS
θJA
Junction-to-ambient thermal resistance(2)
231.2
θJCtop
Junction-to-case (top) thermal resistance(3)
61.8
θJB
Junction-to-board thermal resistance(4)
78.8
°C/W
ψJT
Junction-to-top characterization parameter(5)
2.2
ψJB
Junction-to-board characterization parameter(6)
78
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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