Pin Name

I/O

No.

Description

PLL GND

I

2

Ground pins for PLL

LVDS V

CC

I

1

Power supply pin for LVDS outputs

LVDS GND

I

3

Ground pins for LVDS outputs

DS90CF564 Pin Descriptions — FPD Link Receiver

Pin Name

I/O

No.

Description

RxIN+

I

3

Positive LVDS differential data inputs

RxIN−

I

3

Negative LVDS differential data inputs

RxOUT

O

21

TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME, DRDY(also referred to as HSYNC, VSYNC, Data Enable)

RxCLK IN+

I

1

Positive LVDS differential clock input

RxCLK IN−

I

1

Negative LVDS differential clock input

FPSHIFT

OUT

O

1

TTL level clock output. The falling edge acts as data strobe

PWR DOWN

I

1

TTL level input. Assertion (low input) maintains the receiver outputs in the previous state

V

CC

I

4

Power supply pins for TTL outputs

GND

I

5

Ground pins for TTL outputs

PLL V

CC

I

1

Power supply for PLL

PLL GND

I

2

Ground pin for PLL

LVDS V

CC

I

1

Power supply pin for LVDS inputs

LVDS GND

I

3

Ground pins for LVDS inputs

Connection Diagrams

DS90CF563

DS012615-22

DS90CF564

DS012615-23

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