FLASH MEMORY

10

Preliminary

K9F2G08Q0M K9F2G16Q0M

K9F2G08U0M K9F2G16U0M

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

-

10

pF

Input Capacitance

-

10

pF

VALID BLOCK

NOTE :

1. The

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

. Do not erase or pro-

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase

cycles.

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

2,008

-

2,048

Blocks

AC TEST CONDITION

(K9F2GXXX0M-XCB0 :TA=0 to 70

°C, K9F2GXXX0M-XIB0:TA=-40 to 85°C

K9F2GXXQ0M : Vcc=1.70V~1.95V , K9F2GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)

Parameter

K9F2GXXQ0M

K9F2GXXU0M

Input Pulse Levels

0V to Vcc

0V to Vcc

Input Rise and Fall Times

5ns

5ns

Input and Output Timing Levels

Vcc/2

Vcc/2

Output Load

1 TTL GATE and CL=30pF

1 TTL GATE and CL=50pF

Program / Erase Characteristics

NOTE : 1. Max. time of

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

-

300

700

µs

Dummy Busy Time for Cache Program

3

700

µs

Number of Partial Program Cycles

in the Same Page

Main Array

Nop

-

-

4

cycles

Spare Array

-

-

4

cycles

Block Erase Time

-

2

3

ms

MODE SELECTION

2. WP and PRE should be biased to CMOS high or CMOS low for standby.

CLE

ALE

CE

WE

RE

WP

PRE

Mode

H

L

L

H

X

X

Read Mode

Command Input

L

H

L

H

X

X

Address Input(5clock)

H

L

L

H

H

X

Write Mode

Command Input

L

H

L

H

H

X

Address Input(5clock)

L

L

L

H

H

X

Data Input

L

L

L

H

X

X

Data Output

X

X

X

X

H

X

X

During Read(Busy)

X

X

X

X

X

H

X

During Program(Busy)

X

X

X

X

X

H

X

During Erase(Busy)

X

X

X

X

L

X

Write Protect

X

X

H

X

X

Stand-by