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K4D551638F-TC50 Datasheet(PDF) 7 Page - Samsung semiconductor |
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K4D551638F-TC50 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 16 page 256M GDDR SDRAM K4D551638F-TC - 7 - Rev 1.7 (June 2004) Target Spec • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. FUNCTIONAL DESCRIPTION Power up & Initialization Sequence Command 0 12 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP 2 Clock min. precharge ALL Banks 2nd Auto Refresh Mode Register Set Any Command tRFC 1st Auto Refresh tRFC EMRS MRS 2 Clock min. DLL Reset precharge ALL Banks tRP Inputs must be stable for 200us 200 Clock min. 2 Clock min. CK,CK 메마른 뼈들에 생기를 주닮도록 ( 주수아 ) 하나님의 마음 ( 주찬양 ) Day of Eligah * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. |
Similar Part No. - K4D551638F-TC50 |
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Similar Description - K4D551638F-TC50 |
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