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GS1661A Datasheet(PDF) 10 Page - Semtech Corporation

Part # GS1661A
Description  HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS1661A Datasheet(HTML) 10 Page - Semtech Corporation

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GS1661A HD/SD SDI Receiver
Data Sheet
54387 - 2
September 2012
10 of 85
E7
SDOUT_TDO
Output
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
Note: GSPI is slightly different than the SPI. For more details on GSPI,
please refer to 4.18 GSPI - HOST Interface.
E8
SDIN_TDI
Input
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
F1, G1AGCP, AGCNAutomatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
F7
CS_TMS
Input
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used
to control the operation of the JTAG test.
In host interface mode (JTAG/HOST = LOW), this pin operates as the
host interface chip select and is active LOW.
F8
SCLK_TCK
Input
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Serial data clock signal.
In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG/HOST = LOW), this pin is the host
interface serial bit clock.
All JTAG/host interface addresses and data are shifted into/out of
the device synchronously with this clock.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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