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DS90CF384A Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. DS90CF384A
Description  3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS90CF384A Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
ICCRZ
Receiver Supply Current
Power Down
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
10
55
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ∆V OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4 )
25
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4 )
1.8
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 11,
Figure 12 )
f = 65 MHz
0.7
1.1
1.4
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6
Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin (Note 4) (Figure 13 )
f = 65 MHz
400
ps
RCOP
RxCLK OUT Period (Figure 5)
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 5 )
f = 65 MHz
5.0
7.6
9.0
ns
RCOL
RxCLK OUT Low Time (Figure 5)
5.0
6.3
9.0
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 5 )
4.5
7.3
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 5 )
4.0
6.3
ns
RCCD
RxCLK IN to RxCLK OUT Delay @ 25˚C, V
CC = 3.3V (Figure 6 )
3.5
5.0
7.5
ns
RPLLS
Receiver Phase Lock Loop Set (Figure 7 )
10
ms
RPDD
Receiver Power Down Delay (Figure 10 )
1µs
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383A transmitter pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different transmitters are
used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
www.national.com
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