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IDT7008L25PF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT7008L25PF
Description  HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
Download  19 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7008L25PF Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
6. Refer to Chip Enable Truth Table.
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
3198 drw 06
893
Ω
30pF
347
Ω
5V
DATAOUT
BUSY
INT
893
Ω
5pF*
347
Ω
5V
DATAOUT
3198 drw 05
tRC
R/
W
CE(6)
ADDR
tAA
OE
3198 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
CE
3198 drw 08
tPU
ICC
ISB
tPD
(6)
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
3198 tbl 11


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