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IDT71V546 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT71V546
Description  128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71V546 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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©1999 Integrated Device Technology, Inc.
DECEMBER 1999
DSC-3821/03
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Pin Description Summary
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
Features
x
x
x
x
x
128K x 36 memory configuration, pipelined outputs
x
x
x
x
x
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
x
x
x
x
x
ZBTTM Feature - No dead cycles between write and read
cycles
x
x
x
x
x
Internally synchronized registered outputs eliminate the
need to control
OE
x
x
x
x
x
Single R/
W (READ/WRITE) control pin
x
x
x
x
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
x
x
x
x
4-word burst capability (interleaved or linear)
x
x
x
x
x
Individual byte write (
BW1 - BW4) control (May tie active)
x
x
x
x
x
Three chip enables for simple depth expansion
x
x
x
x
x
Single 3.3V power supply (±5%)
x
x
x
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x
Packaged in a JEDEC standard 100-pin TQFP package
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (
CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when
CENishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (
CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
when ADV/
LDislow,nonewmemoryoperationcanbeinitiatedandany
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented
to the SRAM. The order of the burst sequence is defined by the
LBOinput
pin. The
LBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/
LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/
LD = HIGH).
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
IDT71V546
128K x 36, 3.3V Synchronous
SRAM with ZBT
™ Feature,
Burst Counter and Pipelined Outputs
A0 - A16
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Three Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance Burst Address / Load New Address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
I/O0 - I/O31, I/OP1 - I/OP4
Data Input/Output
I/O
Synchronous
VDD
3.3V Power
Supply
Static
VSS
Ground
Supply
Static
3821 tbl 01


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