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IDT71V546 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT71V546
Description  128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71V546 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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6.42
5
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/
LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/
W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (
CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When
CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires
CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
CEN
R/
W
Chip
(5)
Enable
ADV/
LD
BWx
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D
(7)
L
H
Select
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE/
BURST WRITE
BURST WRITE
(Advance Burst Counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ/
BURST READ
BURST READ
(Advance Burst Counter)(2)
Q(7)
L
X
Deselect
L
X
X
X
DESELECT or STOP(3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
XXX
X
SUSPEND(4)
Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Operation
R/
W
BW1
BW2
BW3
BW4
READ
H
X
XXX
WRITE ALL BYTES
L
L
L
L
L
WRITE BYTE 1 (I/O [0:7], I/OP1)(2)
LL
H
H
H
WRITE BYTE 2 (I/O [8:15], I/OP2)(2)
LH
LH
H
WRITE BYTE 3 (I/O [16:23], I/OP3)(2)
LH
H
L
H
WRITE BYTE 4 (I/O [24:31], I/OP4)(2)
LH
H
H
L
NO WRITE
L
HH
HH
3821 tbl 08


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