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DS1744WP-120IND Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS1744WP-120IND Datasheet(HTML) 3 Page - Dallas Semiconductor |
3 / 18 page DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs 3 of 18 Figure 1. Block Diagram PACKAGES The DS1744 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1744P after the completion of the surface-mount process. Mounting the PowerCap after the surface- mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register (Table 2). As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is, day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All the DS1744 registers are updated simultaneously after the internal clock-register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a 0 for a minimal of 500 ms to ensure the external registers are updated. |
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