CY25100
Document #: 38-07499 Rev. *D
Page 4 of 11
Absolute Maximum Rating
Supply Voltage (VDD) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing).....–55
°C to +125°C
Junction Temperature ................................ –40
°C to +125°C
Data Retention @ Tj = 125
°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
Description
Comments
Min. Typ. Max. Unit
FNOM
Nominal Crystal Frequency
Parallel resonance, fundamental mode, AT cut
8
–
30
MHz
CLNOM
Nominal Load Capacitance
Internal load caps
6
–
30
pF
R1
Equivalent Series Resistance (ESR)
Fundamental mode
–
–
25
Ω
R3/R1
Ratio of Third Overtone Mode ESR to
Fundamental Mode ESR
Ratio used because typical R1 values are much
less than the maximum spec
3–
–
–
DL
Crystal Drive Level
No external series resistor assumed
–
0.5
2
mW
Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
3.13
3.30
3.45
V
TA
Ambient Commercial Temperature
0
–
70
°C
Ambient Industrial Temperature
–40
–
85
°C
CLOAD
Max. Load Capacitance @ pin 6 and pin 7
–
–
15
pF
Fref
External Reference Crystal
(Fundamental tuned crystals only)
8–
30
MHz
External Reference Clock
8
–
166
MHz
FSSCLK
SSCLK output frequency, CLOAD = 15 pF
3
–
200
MHz
FREFCLK
REFCLK output frequency, CLOAD = 15 pF
8
–
166
MHz
FMOD
Spread Spectrum Modulation Frequency
30.0
31.5
33.0
kHz
TPU
Power-up time for all VDDs to reach minimum spec-
ified voltage (power ramp must be monotonic)
0.05
–
500
ms
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V (source)
10
12
mA
IOL
Output Low Current
VOL = 0.5, VDD= 3.3V (sink)
10
12
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7VDD
–VDD
V
VIL
Input Low Voltage
CMOS levels, 30% of VDD
––
0.3VDD
V
IIH
Input High Current, PD#/OE and
SSON# pins
Vin = VDD
––
10
µA
IIL
Input Low Current, PD#/OE and
SSON# pins
Vin = VSS
––
10
µA
IOZ
Output Leakage Current
Three-state output, PD#/OE = 0
–10
10
µA
CXIN or CXOUT[1]
Programmable Capacitance at pin
2 and pin 3
Capacitance at minimum setting
–
12
–
pF
Capacitance at maximum setting
–
60
–
pF
CIN[1]
Input Capacitance at pin 4 and pin
8
Input pins excluding XIN and XOUT
–
5
7
pF
IVDD
Supply Current
VDD = 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
CLOAD = 15 pF, PD#/OE = SSON# = VDD
–25
35
mA
IDDS
Standby current
VDD = 3.45V, Device powered down with
PD# = 0V (driven reference pulled down)
–15
30
µA
Notes:
1. Guaranteed by characterization, not 100% tested.
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