6 / 11 page
CY25100
Document #: 38-07499 Rev. *D
Page 6 of 11
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
t1A
t1B
OUTPUT
Output Rise/Fall Time (SSCLK and REFCLK)
OUTPUT
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
CLKOUT
VDD
tPU
tSTP
VIL
VIH
POWER-
DOWN
0V
(Asynchronous)
High Impedance
Output Enable/Disable Timing
CLKOUT
VDD
TOE1
VIL
VIH
OUTPUT
ENABLE
0V
(Asynchronous)
High Impedance
TOE2