1 of 3

041802

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about DS5240 device

errata, contact the factory.

FEATURES

§

Security features

− Designed to meet the physical security requirements

of FIPS140 and Common Criteria certifications

− Fine-line, top-level metal pattern detects intrusion of

the chip’s cryptographic boundary

− Additional on-chip sensors detect out-of-range

environmental conditions that generate a tamper

response

− The equipment enclosure can be monitored by

tamper response inputs for added protection

− Fast write SRAM technology causes rapid

“zeroization” of secure information as a tamper

response

− Eavesdropping on the external memory bus

prevented by single or triple -DES encryption of the

programs

− Internal chip clock isolated from external system

clock by phase-locked loop

− Asynchronous internal ring oscillator provides clock

for arithmetic operations

− Resources inside cryptographic boundary include:

− Modulo Arithmetic Accelerator (MAA) for up to

4096-bit (e.g., PKI)

− DES and 112-bit key triple-DES engines

available for secret key cryptography

− Random number generator

− Memory Management Unit and 1kB cache

− Firmware bootstrap loader resides in a 16kB

factory-programmed ROM

§

8051 compatible with expanded addressing

− Linear address space directly accesses up to 8MB

of external memory

− Dedicated memory and parallel I/O bus saves port

pins

§

Advanced features

− CRC-16/32 generator provides strong error

detection of memory contents

− True-time clock with alarm interrupt and wake-up

− 5kB internal SRAM with 1kB that can be allocated

to a stack for high-level language support

− Programmable length MOVX instructions allow a

combination of fast and slow devices

− On-chip power detection/selection circuits provide

power-up/down processor reset and early-warning

power-fail interrupt

− Watchdog timer

§

Proven 4-clock/machine cycle architecture

− Single-cycle instruction executes in 160ns

− Runs up to 25MHz clock rates

− Dual data pointers can increment or decrement

independently

DS5240

High-Speed Secure Microcontroller

An NDA is required for full disclosure of details. Contact factory.

www.maxim-ic.com

DS5240

(Top View)

1

100

30

31

50

51

80

81

100-pin QFP

DS5240

(Top View)

80-pin QFP

1

24

25

40

41

64

65

80