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TPS54495RSAT Datasheet(PDF) 5 Page - Texas Instruments |
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TPS54495RSAT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 23 page  SW1 VIN1 VBST 1 EN1 VFB2 VFB1 GND VREG5 PGND1 6 VIN2 VBST2 EN2 SW 2 SS1 5 1 3 SS2 9 10 11 PGND 2 2 4 7 13 12 14 8 15 16 TPS54495 HTSSOP16 PowerPAD PowerPAD VFB1 VFB2 VIN1 VBST2 VBST1 14 7 5 6 2 3 4 1 VIN2 13 12 11 9 8 10 GND 16 15 VREG5 TPS54495 www.ti.com SLVSBH0A – JUNE 2012 – REVISED MAY 2013 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) RSA PACKAGE (TOP VIEW) PIN FUNCTIONS(1) PIN I/O DESCRIPTION NAME PWP RSA VIN1 1 3 I Power inputs and connects to both high side NFET drains. Supply Input for 5.5 V linear regulator. VIN2 16 2 I VBST1 2 4 I Supply input for high-side NFET gate drive circuit. Connect 0.1 µF ceramic capacitor between VBSTx and SWx pins. An internal diode is connected VBST2 15 1 I between VREG5 and VBSTx SW1 3 5 I/O Switch node connections for both the high-side NFETs and low–side NFETs. Input of current comparator. SW2 14 16 I/O PGND1 4 6 I/O Ground returns for low-side MOSFETs. Input of current comparator. PGND2 13 15 I/O EN1 5 7 I Enable. Pull High to enable according converter. EN2 12 14 I SS1 6 8 O Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program Soft-Start time. SS2 11 13 O VFB1 7 9 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider. VFB2 10 12 I Signal GND. Connect sensitive SSx and VFBx returns to GND at a single GND 8 10 I/O point. Output of 5.5 V linear regulator. Bypass to GND with a high-quality ceramic VREG5 9 11 O capacitor of at least 1 µF. VREG5 is active when VIN1 is added. Exposed Thermal Thermal pad of the package. Must be soldered to achieve appropriate Back side Back side I/O Pad dissipation. Must be connected to GND. (1) x means either 1 or 2, that is. VFBx means VFB1 or VFB2. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS54495 |
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