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TPS54372-Q1 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS54372-Q1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 17 page  TPS54372-Q1 SGLS267E − OCTOBER 2004 − REVISED JUNE 2008 www.ti.com 8 OUTPUT FILTER The output filter is composed of a 1- µH inductor and two 150- µF capacitors. The inductor is a low dc resistance (0.010 Ω) type, Vishay IHLP−2525CZ−01 1-µH, 8.5-A rated dc output. The capacitors used are 150 µF, 6.3-V special polymer types. GROUNDING AND PowerPAD LAYOUT The TPS54372 has two internal grounds (analog and power). Inside the TPS54372, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54372, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground areas are recommended. The analog ground area should be tied to the power ground area directly at the IC to reduce noise between the two grounds. The only components that should tie directly to the power ground area are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54372. The power ground areas as well as the powerpad mounting area should be tied to any internal ground planes using multiple vias. The layout of the TPS54372 evaluation module is representative of a recommended layout for a 2-layer board with the bottom layer representing the system ground plane. Documentation for the TPS54372 evaluation module can be found on the Texas Instruments web site under the TPS54372 product folder. LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. Minimum Recommended Exposed Copper Area For PowerPAD. 5mm Stencils may Require 10 Percent Larger Area 0.2454 0.0150 0.06 0.0256 0.1700 0.1340 0.0620 0.0400 0.0400 0.0400 0.0600 0.0227 0.0600 0.1010 6 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance Minimum Recommended Top Side Analog Ground Area Minimum Recommended Thermal Vias: 6 × .013 dia. Inside PowerPAD Area 4 × .018 dia. Under Device as Shown. Additional .018 dia. Vias May be Used if Top Side Analog Ground Area is Extended. 0.2560 Figure 9. Recommended Land Pattern for 20-Pin PWP PowerPAD |
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Similar Description - TPS54372-Q1 |
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