CY2907
Document #: 38-07137 Rev. **
Page 3 of 10
Operating Conditions[3]
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage, 5V Operation
4.5
5.5
V
Supply Voltage, 3.3V Operation
3.0
3.6
V
TA
Commercial Operating Temperature, Ambient
0
70
°C
Industrial Operating Temperature, Ambient
–40
85
°C
CL
Max. Capacitive Load
15
pF
fREF
External Reference Crystal
10.0
25.0
MHz
External Reference Clock[4, 5]
1.0
30.0
MHz
Electrical Characteristics at 5.0V Commercial VDD = 4.5V to 5.5V, TA = 0°C to +70°C
Parameter
Description
Test Conditions
Min.
Max.
Unit
VIH
High-level Input Voltage
Except Crystal Inputs
2.0
V
VIL
Low-level Input Voltage
Except Crystal Inputs
0.8
V
VOH
[4]
High-level Output Voltage
VDD = VDD Min. IOH = –30 mA
CLKA
2.4
V
VOL
[4]
Low-level Output Voltage
VDD = VDD Min. IOL = 10 mA
CLKA
0.4
V
IOH
[4]
Output High Current
VOH = 2.0V
–35
mA
IOL
[4]
Output Low Current
VOL = 0.8V
22
mA
IIH
Input High Current
VIH = VDD
–2
2
µA
IIL
Input Low Current
VIL = 0V
20
µA
IDD
[5]
Power Supply Current
PD HIGH, CLKA = 50 MHz
42
mA
IDD
Power Supply Current
PD LOW, Logic Inputs LOW
100
µA
IDD
Power Supply Current
PD LOW, Logic Inputs HIGH
40
µA
RPU
[4]
Pull-up Resistor
VIN = VDD – 1.0 V
700
k
Ω
Electrical Characteristics at 3.3V Commercial VDD = 3.0V to 3.6V, TA = 0°C to +70°C
Parameter
Description
Test Conditions
Min.
Max.
Unit
VIH
High-level Input Voltage
Except Crystal Inputs
0.7*VDD
V
VIL
Low-level Input Voltage
Except Crystal Inputs
0.2*VDD
V
VOH
[4]
High-level Output Voltage
CLKA, IOH = –5 mA
0.85*VDD
V
VOL
[4]
Low-level Output Voltage
CLKA, IOL = 6 mA
0.1*VDD
V
IOH
[4]
Output High Current
VOH = 0.7*VDD
–10
mA
IOL
[4]
Output Low Current
VOL = 0.2*VDD
15
mA
IIH
Input High Current
VIH = VDD
–2
2
µA
IIL
Input Low Current
VIL = 0V
10
µA
IDD
[5]
Power Supply Current
PD HIGH, CLKA = 50 MHz
40
mA
IDD
Power Supply Current
PD LOW, Logic Inputs LOW
40
µA
IDD
Power Supply Current
PD LOW, Logic Inputs HIGH
12
µA
RPU
[4]
Pull-up Resistor
VIN = VDD – 0.5V
900
k
Ω
Notes:
3.
Electrical parameters are guaranteed with these operating conditions.
4.
Guaranteed by design, not 100% tested in production.
5.
Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:
IDD (mA) = VDD * (6.25 + (0.055*FREF) + (0.0017*CLOAD*(FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz.