Field- and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
CY25100
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07499 Rev. *D
Revised March 24, 2004
Features
• Wide operating output (SSCLK) frequency range
— 3–200 MHz
• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
• Input frequency range
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Field-programmable
— CY25100SCF and CY25100SIF, 8-pin SOIC
— CY25100ZCF and CY25100ZIF, 8-pin TSSOP
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle jitter
• 3.3V operation
• Commercial and Industrial operation
• Spread Spectrum On/Off function
• Power-down or Output Enable function
Benefits
• Services most PC peripherals, networking, and consumer
applications.
• Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC)
requirements. Reduces development and manufacturing
costs and time-to-market.
• Eliminates the need for expensive and difficult to use
higher-order crystals.
• Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
• In-house programming of samples and prototype quantities
is available using the CY3672 programming kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s
value-added distribution partners or by using third-party
programmers from BP Microsystems, HiLo Systems, and
others.
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Suitable for most PC, consumer, and networking applica-
tions
• Application compatibility in standard and low-power
systems
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
PLL
with
MODULATION
CONTROL
PROGRAMMABLE
CONFIGURATION
OUTPUT
DIVIDERS
and
MUX
3
2
4
8
1
5
7
6
VDD
VSS
REFCLK
SSCLK
XOUT
XIN
PD# or OE
SSON#
RFB
CXOUT
CXIN
4
8
VDD
6
7
VSS
REFCLK
SSON#
1
2
3
XOUT
XIN/CLKIN
PD#/OE
SSCLK
5
Pin Configuration
CY25100
8-pin SOIC/TSSOP
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