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TPS54316MPWPREP Datasheet(PDF) 11 Page - Texas Instruments |
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TPS54316MPWPREP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 21 page www.ti.com Slow-Start/Enable (SS/ENA) t d + C (SS) 1.2 V 5 mA (2) t (SS) + C (SS) 0.7 V 5 mA (3) VBIAS Regulator (VBIAS) Voltage Reference TPS54311-EP, TPS54312-EP, TPS54313-EP, TPS54314-EP, TPS54315-EP, TPS54316-EP SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007 PERFORMANCE GRAPHS (continued) The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5- µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. DEVICE OUTPUT VOLTAGE SLOW START TPS54311 0.9 V 3.3 ms TPS54312 1.2 V 4.5 ms TPS54313 1.5 V 5.6 ms TPS54314 1.8 V 3.3 ms TPS54315 2.5 V 4.7 ms TPS54316 3.3 V 6.1 ms The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal rate. The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54311-16, since it cancels offset errors in the scale and error amplifier circuits. 11 Submit Documentation Feedback |
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