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5962-9675801QXA Datasheet(PDF) 5 Page - Texas Instruments |
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5962-9675801QXA Datasheet(HTML) 5 Page - Texas Instruments |
5 / 97 page vi List of Tables Table Title Page 2–1 Direct Register Map 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Indirect Register Map (Extended Registers) 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Allocation of Palette Page Register Bits† 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Color Register Address Format 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Clock Selection Register Bits CSR(6 – 4)(Index: 0x1A, Access: R/W, Default: 0x07) 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Clock Selection Register Bits CSR(3 – 0) (Index: 0x1A, Access: R/W, Default: 0x07) 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 PLL Top-Level Registers 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 PLL Address Register (Index: 0x2C, Access: R/W, Default: Uninitialized) 2–7 . . . . . . . 2–9 PLL Data Register Pointer Format 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Pixel Clock PLL Registers† 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Pixel Clock PLL Frequency Selection 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 MCLK PLL Registers† 2–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 MCLK/Loop Clock Control Register (Index: 0x39 hex, Access: R/W, Default:0x18) 2–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Loop Clock PLL Registers 2–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Loop Clock PLL Settings for Packed-24 Mode 2–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Latch-Control Register (Index: 0x0F, Access: R/W, Default: 0x06) 2–15 . . . . . . . . . . . . 2–17 Multiplex Mode and Bus Width Selection 2–24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Pseudo-Color Mode Pixel-Latching Sequence 2–27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Packed-24 Formats 2–28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20 Direct-Color Mode Pixel-Latching Sequence (Little-Endian) 2–29 2–21 Direct-Color Mode Pixel-Latching Sequence (Big-Endian) 2–30 . . . . . . . . . . . . . . . . . . . 2–22 Cursor RAM Vs. Color Selection 2–33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23 Port-Select Switching 2–35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24 Sense Test Register Results 2–38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25 General-Purpose I/O Registers 2–39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26 General-Control Register 2–42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27 Miscellaneous Control Register 2–42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28 Indirect Cursor-Control Register 2–43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29 Direct Cursor-Control Register 2–43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30 Cursor Position (X, Y) Registers 2–44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31 Color-Key Control Register 2–45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32 Color-Key Low and High Registers 2–46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33 CRC Remainder LSB and MSB Registers 2–46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34 CRC Bit Select Register 2–46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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