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CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 8 of 51
Logic Block Diagram
Interrupt
Controller
PROM
12-bit
Timer
Reset
Watchdog
Timer
Repeater
Power-on
SCLK
I2C comp.
USB
Transceiver
USB
Transceiver
USB
Transceiver
GPIO
PORT 1
GPIO
PORT 0
P0[0]
P0[7]
P1[0]
P1[2]
SDATA
D+[5]
D–[5]
D+[4]
D–[4]
6-MHz crystal
RAM
USB
SIE
USB
Transceiver
D+[7]
D–[7]
USB
Transceiver
D+[0]
D–[0]
D+[1]
D–[1]
Upstream
USB Port
CY7C65013 only
GPIO
PORT 2
P2[7]
P2[3]
256 byte
8 KB
Clock
6 MHz
12-MHz
8-bit
CPU
Power management under firmware
control using GPIO pins
Interface
GPIO
PORT 3
P3[1]
P3[0]
High Current
Outputs
PLL
12 MHz
48 MHz
Divider
Downstream USB Ports
CY7C65013 only
*I2C-compatible interface enabled by firmware through
P2[1:0] or P1[1:0]