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CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 9 of 18
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
Reset Timing
tRS
tRSR
Q0- Q8
RS
tRSF
tRSF
tRSF
OE=1
OE=0
REN1,
REN2
EF,PAE
FF,PAF
tRSS
tRSR
tRSS
tRSR
tRSS
WEN2/LD
WEN1
[16]
[18]
[17]
D0(FIRST VALID WRITE)
First Data Word Latency after Reset with Read and Write
tSKEW1
WEN1
WCLK
Q0 –Q8
EF
REN1,
REN2
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1
D2
D3
D4
D0
D1
D0 –D8
tA
WEN2
(if applicable)
[19]
[20]
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