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C9531 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. C9531
Description  PCIX I/O System Clock Generator with EMI Control Features
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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C9531 Datasheet(HTML) 1 Page - Cypress Semiconductor

 
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PCIX I/O System Clock Generator with EMI Control Features
C9531
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of 5 clocks.
• One REF XIN clock output.
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Note:
1.
XIN is the frequency of the clock on the device’s XIN pin.
Table 1. Test Mode Logic Table[1]
Input Pins
Output Pins
OE
S1
S0
CLK
REF
HIGH
LOW
LOW
XIN
XIN
HIGH
LOW
HIGH
2 * XIN
XIN
HIGH
HIGH
LOW
3 * XIN
XIN
HIGH
HIGH
HIGH
4 * XIN
XIN
LOW
X
X
Three-state Three-state
Block Diagram
Pin Configuration
XIN
CLK3
CLK2
CLK1
CLK0
/N
SSCG#
CLK4
SSCG
Logic
1
0
XOUT
I2C
Control
Logic
SCLK
OE
IA(0:2)
SDATA
GOOD#
REF
S(0,1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
XOUT
VSS
S1
GOOD#
VSS
IA1
IA2
VDDA
OE
IA0
SSCG#
VSS
CLK4
CLK3
VSS
CLK2
VDDA
VDDP
CLK1
CLK0
VDDP
VSS
SCLK
SDATA
REF
S0
XIN


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